DDR Synthesizable Bus Functional Models

The EasyIC synthesizable DDR models are fully functional, configurable and cycle-accurate JEDEC standard based models. They can be targeted to a wide range of emulation systems as well as FPGAs. The synthesizable DDR models enable the users to debug their design in simulations. emulation environments and with FPGAs.

There are currently 4 models available in the library: DDR3, LPDDR3, DDR4 and LPDDR4.

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